ZYNQ PS-PL通信（PL側）

来源:https://www.cnblogs.com/kk76/archive/2022/12/04/16885502.html
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概述 ZYNQ分為PS和PL兩部分，PS端即ARM，PL即FPGA。在使用ZYNQ的時候不免需要PS和PL端進行通信。大多是情況下PS作為主端，PL作為從端，通過AXI匯流排實現PS-PL端的通信。本文主要介紹PL（即FPGA）如何配置的。 Block Design創建 1.點擊Create Bloc ...


概述

 ZYNQ分為PS和PL兩部分，PS端即ARM，PL即FPGA。在使用ZYNQ的時候不免需要PS和PL端進行通信。大多是情況下PS作為主端，PL作為從端，通過AXI匯流排實現PS-PL端的通信。本文主要介紹PL（即FPGA）如何配置的。

Block Design創建

　　1.點擊Create Block Design，添加ZYNQ7 Processing System IP

 

　　2.雙擊打開ZYNQ7 Processing System，下圖所示表示PS作為主端的介面。

 

 

　　3.加入AXI Interconnect IP，由於上一步只設置了一個主端，所以Slave和Master都需要設置為1

 

 

 接下來就需要AXI_Lite介面，這個可以自己寫，官方也提供了模板。接下來就詳細說明官方模板

AXI_Lite創建

　　1.點擊Tool > Create and Package New IP > Next，選擇 Create a new AXI4 peripheral > Next

 

 　　2.接下來設置IP的名字和存放地址，然後 next。

 

 

 　　4.接下來設置參數，Number of Registers根據需要設置，其他的不變。設置成64，表示有64個寄存器，每個寄存器的數據位寬是32bit。點擊Next

 

 

 　　5.這裡選擇Edit IP，我們可以對官方的模板進行一些修改。然後點擊Finish會重新打開一個工程，在這個工程中我們可以對官方的模板進行修改。

 

 

 

AXI-Lite官方模板說明

　　可以看出官方文檔由兩個文件組成，這個官方文檔是實現loopback的，亦是PS對某個寄存器寫下來什麼數據，讀到的就是什麼數據，並沒有給出介面來和PL通信的。接下來將對這兩個代碼進行說明。

 

 

axi_lite_v1_0文件說明

　　這個代碼主要功能是調用了axi_lite_v1_0_S00_AXI模塊。在真實的使用中我們需要進行修改。添加一些信號來和PL通信。

 

 

信號名稱 說明
o_axi_clk AXI-Lite的時鐘
o_axi_rst_n 複位信號
o_rx_addr PS寫寄存器的地址（PS to PL）
o_rx_data PS寫寄存器的數據（PS to PL）
o_rx_data_vld PS寫數據有效（PS to PL）
i_tx_addr PL給PS數據地址
i_tx_data PL給PS的數據
i_tx_data_vld PL給PS數據有效信號

　　時鐘和複位信號直接把輸入的引出就好，其他信號則需要在另一個模塊中處理。

　　　

 

 

 

axi_lite_v1_0_S00_AXI

　　該模塊實現了AXI—Lite，我們需要做一些修改。

　　1.和上一模塊對應，需要添加一些介面。

 

 

 　　2.PS寫寄存器

always @( posedge S_AXI_ACLK )
    begin
      if ( S_AXI_ARESETN == 1'b0 )
        begin
          slv_reg0 <= 0;
          slv_reg1 <= 0;
          slv_reg2 <= 0;
          slv_reg3 <= 0;
          slv_reg4 <= 0;
          slv_reg5 <= 0;
          slv_reg6 <= 0;
          slv_reg7 <= 0;
          slv_reg8 <= 0;
          slv_reg9 <= 0;
          slv_reg10 <= 0;
          slv_reg11 <= 0;
          slv_reg12 <= 0;
          slv_reg13 <= 0;
          slv_reg14 <= 0;
          slv_reg15 <= 0;
          slv_reg16 <= 0;
          slv_reg17 <= 0;
          slv_reg18 <= 0;
          slv_reg19 <= 0;
          slv_reg20 <= 0;
          slv_reg21 <= 0;
          slv_reg22 <= 0;
          slv_reg23 <= 0;
          slv_reg24 <= 0;
          slv_reg25 <= 0;
          slv_reg26 <= 0;
          slv_reg27 <= 0;
          slv_reg28 <= 0;
          slv_reg29 <= 0;
          slv_reg30 <= 0;
          slv_reg31 <= 0;
          slv_reg32 <= 0;
          slv_reg33 <= 0;
          slv_reg34 <= 0;
          slv_reg35 <= 0;
          slv_reg36 <= 0;
          slv_reg37 <= 0;
          slv_reg38 <= 0;
          slv_reg39 <= 0;
          slv_reg40 <= 0;
          slv_reg41 <= 0;
          slv_reg42 <= 0;
          slv_reg43 <= 0;
          slv_reg44 <= 0;
          slv_reg45 <= 0;
          slv_reg46 <= 0;
          slv_reg47 <= 0;
          slv_reg48 <= 0;
          slv_reg49 <= 0;
          slv_reg50 <= 0;
          slv_reg51 <= 0;
          slv_reg52 <= 0;
          slv_reg53 <= 0;
          slv_reg54 <= 0;
          slv_reg55 <= 0;
          slv_reg56 <= 0;
          slv_reg57 <= 0;
          slv_reg58 <= 0;
          slv_reg59 <= 0;
          slv_reg60 <= 0;
          slv_reg61 <= 0;
          slv_reg62 <= 0;
          slv_reg63 <= 0;
        end 
      else begin
        if (slv_reg_wren)
          begin
            case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
              6'h00:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 0
                    slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h01:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 1
                    slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h02:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 2
                    slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h03:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 3
                    slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h04:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 4
                    slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h05:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 5
                    slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h06:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 6
                    slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h07:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 7
                    slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h08:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 8
                    slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h09:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 9
                    slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h0A:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 10
                    slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h0B:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 11
                    slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h0C:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 12
                    slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h0D:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 13
                    slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h0E:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 14
                    slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h0F:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 15
                    slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h10:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 16
                    slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h11:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 17
                    slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h12:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 18
                    slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h13:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 19
                    slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h14:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 20
                    slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h15:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 21
                    slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h16:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 22
                    slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h17:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 23
                    slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h18:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 24
                    slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h19:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 25
                    slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h1A:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 26
                    slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h1B:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 27
                    slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h1C:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 28
                    slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h1D:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 29
                    slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h1E:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 30
                    slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h1F:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 31
                    slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h20:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 32
                    slv_reg32[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h21:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 33
                    slv_reg33[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h22:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 34
                    slv_reg34[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h23:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 35
                    slv_reg35[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h24:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 36
                    slv_reg36[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h25:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 37
                    slv_reg37[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h26:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 38
                    slv_reg38[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h27:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 39
                    slv_reg39[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h28:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 40
                    slv_reg40[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h29:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 41
                    slv_reg41[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h2A:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 42
                    slv_reg42[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h2B:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 43
                    slv_reg43[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h2C:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 44
                    slv_reg44[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h2D:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 45
                    slv_reg45[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h2E:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 46
                    slv_reg46[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h2F:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 47
                    slv_reg47[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h30:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 48
                    slv_reg48[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h31:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 49
                    slv_reg49[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h32:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 50
                    slv_reg50[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h33:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 51
                    slv_reg51[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h34:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 52
                    slv_reg52[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h35:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 53
                    slv_reg53[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h36:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 54
                    slv_reg54[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h37:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 55
                    slv_reg55[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h38:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 56
                    slv_reg56[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h39:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 57
                    slv_reg57[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h3A:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 58
                    slv_reg58[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h3B:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 59
                    slv_reg59[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h3C:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 60
                    slv_reg60[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h3D:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 61
                    slv_reg61[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h3E:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 62
                    slv_reg62[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              6'h3F:
                for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
                  if ( S_AXI_WSTRB[byte_index] == 1 ) begin
                    // Respective byte enables are asserted as per write strobes 
                    // Slave register 63
                    slv_reg63[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                  end  
              default : begin
                          slv_reg0 <= slv_reg0;
                          slv_reg1 <= slv_reg1;
                          slv_reg2 <= slv_reg2;
                          slv_reg3 <= slv_reg3;
                          slv_reg4 <= slv_reg4;
                          slv_reg5 <= slv_reg5;
                          slv_reg6 <= slv_reg6;
                          slv_reg7 <= slv_reg7;
                          slv_reg8 <= slv_reg8;
                          slv_reg9 <= slv_reg9;
                          slv_reg10 <= slv_reg10;
                          slv_reg11 <= slv_reg11;
                          slv_reg12 <= slv_reg12;
                          slv_reg13 <= slv_reg13;
                          slv_reg14 <= slv_reg14;
                          slv_reg15 <= slv_reg15;
                          slv_reg16 <= slv_reg16;
                          slv_reg17 <= slv_reg17;
                          slv_reg18 <= slv_reg18;
                          slv_reg19 <= slv_reg19;
                          slv_reg20 <= slv_reg20;
                          slv_reg21 <= slv_reg21;
                          slv_reg22 <= slv_reg22;
                          slv_reg23 <= slv_reg23;
                          slv_reg24 <= slv_reg24;
                          slv_reg25 <= slv_reg25;
                          slv_reg26 <= slv_reg26;
                          slv_reg27 <= slv_reg27;
                          slv_reg28 <= slv_reg28;
                          slv_reg29 <= slv_reg29;
                          slv_reg30 <= slv_reg30;
                          slv_reg31 <= slv_reg31;
                          slv_reg32 <= slv_reg32;
                          slv_reg33 <= slv_reg33;
                          slv_reg34 <= slv_reg34;
                          slv_reg35 <= slv_reg35;
                          slv_reg36 <= slv_reg36;
                          slv_reg37 <= slv_reg37;
                          slv_reg38 <= slv_reg38;
                          slv_reg39 <= slv_reg39;
                          slv_reg40 <= slv_reg40;
                          slv_reg41 <= slv_reg41;
                          slv_reg42 <= slv_reg42;
                          slv_reg43 <= slv_reg43;
                          slv_reg44 <= slv_reg44;
                          slv_reg45 <= slv_reg45;
                          slv_reg46 <= slv_reg46;
                          slv_reg47 <= slv_reg47;
                          slv_reg48 <= slv_reg48;
                          slv_reg49 <= slv_reg49;
                          slv_reg50 <= slv_reg50;
                          slv_reg51 <= slv_reg51;
                          slv_reg52 <= slv_reg52;
                          slv_reg53 <= slv_reg53;
                          slv_reg54 <= slv_reg54;
                          slv_reg55 <= slv_reg55;
                          slv_reg56 <= slv_reg56;
                          slv_reg57 <= slv_reg57;
                          slv_reg58 <= slv_reg58;
                          slv_reg59 <= slv_reg59;
                          slv_reg60 <= slv_reg60;
                          slv_reg61 <= slv_reg61;
                          slv_reg62 <= slv_reg62;
                          slv_reg63 <= slv_reg63;
                        end
            endcase
          end
      end
    end

　　這一段就是官方模板中PS寫寄存器的代碼。前面定義的就寄存器數量是64，可以看出判斷的時候只用了地址axi_awaddr[7:2]，這是因為數據位寬是32bit，而一個真實的寄存器地址只有8bit的數據，所以地址的偏移量為4。PS也可以只更新某個8bit的寄存器，這個可以S_AXI_WSTRB判斷更新的是哪一個寄存器，一般情況下PS也是32bit一起更新，所以無需使用S_AXI_WSTRB信號。

always @( posedge S_AXI_ACLK )
    begin
      if ( S_AXI_ARESETN == 1'b0 )
        begin
          o_rx_addr        <= 0;
          o_rx_data        <= 0;
          o_rx_data_vld <= 0;
        end 
      else begin
        if (slv_reg_wren)
          begin
            case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
              6'h00: begin
                o_rx_addr        <= 6'h00;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h01: begin
                o_rx_addr        <= 6'h01;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              
              6'h02: begin
                o_rx_addr        <= 6'h02;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h03: begin
                o_rx_addr        <= 6'h03;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h04: begin
                o_rx_addr        <= 6'h04;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h05: begin
                o_rx_addr        <= 6'h05;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h06: begin
                o_rx_addr        <= 6'h06;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h07: begin
                o_rx_addr        <= 6'h07;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h08: begin
                o_rx_addr        <= 6'h08;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h09: begin
                o_rx_addr        <= 6'h09;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h0A: begin
                o_rx_addr        <= 6'h0A;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h0B: begin
                o_rx_addr        <= 6'h0B;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h0C: begin
                o_rx_addr        <= 6'h0C;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h0D: begin
                o_rx_addr        <= 6'h0D;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h0E: begin
                o_rx_addr        <= 6'h0E;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h0F: begin
                o_rx_addr        <= 6'h0F;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h10: begin
                o_rx_addr        <= 6'h10;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h11: begin
                o_rx_addr        <= 6'h11;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;  
              end
              6'h12: begin
                o_rx_addr        <= 6'h12;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h13: begin
                o_rx_addr        <= 6'h13;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h14: begin
                o_rx_addr        <= 6'h14;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;  
              end
              6'h15: begin
                o_rx_addr        <= 6'h15;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;  
              end
              6'h16: begin
                o_rx_addr        <= 6'h16;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h17: begin
                o_rx_addr        <= 6'h17;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;  
              end
              6'h18: begin
                o_rx_addr        <= 6'h18;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h19: begin
                o_rx_addr        <= 6'h19;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h1A: begin
                o_rx_addr        <= 6'h1A;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h1B: begin
                o_rx_addr        <= 6'h1B;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;   
              end
              6'h1C: begin
                o_rx_addr        <= 6'h1C;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h1D: begin
                o_rx_addr        <= 6'h1D;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h1E: begin
                o_rx_addr        <= 6'h1E;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h1F: begin
                o_rx_addr        <= 6'h1F;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h20: begin
                o_rx_addr        <= 6'h20;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h21: begin
                o_rx_addr        <= 6'h21;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h22: begin
                o_rx_addr        <= 6'h22;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h23: begin
                o_rx_addr        <= 6'h23;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h24: begin
                o_rx_addr        <= 6'h24;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h25: begin
                o_rx_addr        <= 6'h25;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h26: begin
                o_rx_addr        <= 6'h26;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h27: begin
                o_rx_addr        <= 6'h27;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h28: begin
               o_rx_addr        <= 6'h28;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h29: begin
                o_rx_addr        <= 6'h29;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h2A: begin
                o_rx_addr        <= 6'h2A;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h2B: begin
                o_rx_addr        <= 6'h2B;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h2C: begin
                o_rx_addr        <= 6'h2C;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h2D: begin
                o_rx_addr        <= 6'h2D;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h2E: begin
                o_rx_addr        <= 6'h2E;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h2F: begin
                o_rx_addr        <= 6'h2F;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h30: begin
                o_rx_addr        <= 6'h30;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h31: begin
                o_rx_addr        <= 6'h31;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h32: begin
                o_rx_addr        <= 6'h32;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h33: begin
                o_rx_addr        <= 6'h33;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h34: begin
                o_rx_addr        <= 6'h34;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h35: begin
                o_rx_addr        <= 6'h35;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h36: begin
                o_rx_addr        <= 6'h36;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h37: begin
                o_rx_addr        <= 6'h37;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h38: begin
                o_rx_addr        <= 6'h38;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h39: begin
                o_rx_addr        <= 6'h39;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h3A: begin
                o_rx_addr        <= 6'h3A;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h3B: begin
                o_rx_addr        <= 6'h3B;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1; 
              end
              6'h3C: begin
                o_rx_addr        <= 6'h3C;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h3D: begin
                o_rx_addr        <= 6'h3D;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h3E: begin
                o_rx_addr        <= 6'h3E;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              6'h3F: begin
                o_rx_addr        <= 6'h3F;
                o_rx_data        <= S_AXI_WDATA;
                o_rx_data_vld     <= 1'b1;
              end
              default : begin
                          o_rx_addr        <= 6'h3F;
                          o_rx_data        <= S_AXI_WDATA;
                          o_rx_data_vld <= 1'b0;
                        end
            endcase
          end
          else begin
            o_rx_addr        <= 6'h00;
            o_rx_data        <= S_AXI_WDATA;
            o_rx_data_vld     <= 1'b0;
          end
      end
    end

 

　　3.PS讀寄存器

　　官方模板中PS讀寄存器代買如下。原本slv_reg的值為PS寫的值。

always @(*)
    begin
          // Address decoding for reading registers
          case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
            6'h00   : reg_data_out <= slv_reg0;
            6'h01   : reg_data_out <= slv_reg1;
            6'h02   : reg_data_out <= slv_reg2;
            6'h03   : reg_data_out <= slv_reg3;
            6'h04   : reg_data_out <= slv_reg4;
            6'h05   : reg_data_out <= slv_reg5;
            6'h06   : reg_data_out <= slv_reg6;
            6'h07   : reg_data_out <= slv_reg7;
            6'h08   : reg_data_out <= slv_reg8;
            6'h09   : reg_data_out <= slv_reg9;
            6'h0A   : reg_data_out <= slv_reg10;
            6'h0B   : reg_data_out <= slv_reg11;
            6'h0C   : reg_data_out <= slv_reg12;
            6'h0D   : reg_data_out <= slv_reg13;
            6'h0E   : reg_data_out <= slv_reg14;
            6'h0F   : reg_data_out <= slv_reg15;
            6'h10   : reg_data_out <= slv_reg16;
            6'h11   : reg_data_out <= slv_reg17;
            6'h12   : reg_data_out <= slv_reg18;
            6'h13   : reg_data_out <= slv_reg19;
            6'h14   : reg_data_out <= slv_reg20;
            6'h15   : reg_data_out <= slv_reg21;
            6'h16   : reg_data_out <= slv_reg22;
            6'h17   : reg_data_out <= slv_reg23;
            6'h18   : reg_data_out <= slv_reg24;
            6'h19   : reg_data_out <= slv_reg25;
            6'h1A   : reg_data_out <= slv_reg26;
            6'h1B   : reg_data_out <= slv_reg27;
            6'h1C   : reg_data_out <= slv_reg28;
            6'h1D   : reg_data_out <= slv_reg29;
            6'h1E   : reg_data_out <= slv_reg30;
            6'h1F   : reg_data_out <= slv_reg31;
            6'h20   : reg_data_out <= slv_reg32;
            6'h21   : reg_data_out <= slv_reg33;
            6'h22   : reg_data_out <= slv_reg34;
            6'h23   : reg_data_out <= slv_reg35;
            6'h24   : reg_data_out <= slv_reg36;
            6'h25   : reg_data_out <= slv_reg37;
            6'h26   : reg_data_out <= slv_reg38;
            6'h27   : reg_data_out <= slv_reg39;
            6'h28   : reg_data_out <= slv_reg40;
            6'h29   : reg_data_out <= slv_reg41;
            6'h2A   : reg_data_out <= slv_reg42;
            6'h2B   : reg_data_out <= slv_reg43;
            6'h2C   : reg_data_out <= slv_reg44;
            6'h2D   : reg_data_out <= slv_reg45;
            6'h2E   : reg_data_out <= slv_reg46;
            6'h2F   : reg_data_out <= slv_reg47;
            6'h30   : reg_data_out <= slv_reg48;
            6'h31   : reg_data_out <= slv_reg49;
            6'h32   : reg_data_out <= slv_reg50;
            6'h33   : reg_data_out <= slv_reg51;
            6'h34   : reg_data_out <= slv_reg52;
            6'h35   : reg_data_out <= slv_reg53;
            6'h36   : reg_data_out <= slv_reg54;
            6'h37   : reg_data_out <= slv_reg55;
            6'h38   : reg_data_out <= slv_reg56;
            6'h39   : reg_data_out <= slv_reg57;
            6'h3A   : reg_data_out <= slv_reg58;
            6'h3B   : reg_data_out <= slv_reg59;
            6'h3C   : reg_data_out <= slv_reg60;
            6'h3D   : reg_data_out <= slv_reg61;
            6'h3E   : reg_data_out <= slv_reg62;
            6'h3F   : reg_data_out <= slv_reg63;
            default : reg_data_out <= 0;
          endcase
    end

 

在後面增加一段代碼，將PL要發送給PS的數據，給到slv_reg*。（由於PS是主端，只有PS主動讀某個寄存器地址後，才能完成PL發送給PS）。

 

    // Add user logic here
    always @( posedge S_AXI_ACLK )
    begin
      if ( S_AXI_ARESETN == 1'b0 )
        begin
          slv_reg0    <= 0;
          slv_reg1    <= 0;
          slv_reg2    <= 0;
          slv_reg3    <= 0;
          slv_reg4    <= 0;
          slv_reg5    <= 0;
          slv_reg6    <= 0;
          slv_reg7    <= 0;
          slv_reg8    <= 0;
          slv_reg9  <= 0;
          slv_reg10 <= 0;
          slv_reg11 <= 0;
          slv_reg12 <= 0;
          slv_reg13 <= 0;
          slv_reg14 <= 0;
          slv_reg15 <= 0;
          slv_reg16 <= 0;
          slv_reg17 <= 0;
          slv_reg18 <= 0;
          slv_reg19 <= 0;
          slv_reg20 <= 0;
          slv_reg21 <= 0;
          slv_reg22 <= 0;
          slv_reg23 <= 0;
          slv_reg24 <= 0;
          slv_reg25 <= 0;
          slv_reg26 <= 0;
          slv_reg27 <= 0;
          slv_reg28 <= 0;
          slv_reg29 <= 0;
          slv_reg30 <= 0;
          slv_reg31 <= 0;
          slv_reg32 <= 0;
          slv_reg33 <= 0;
          slv_reg34 <= 0;
          slv_reg35 <= 0;
          slv_reg36 <= 0;
          slv_reg37 <= 0;
          slv_reg38 <= 0;
          slv_reg39 <= 0;
          slv_reg40 <= 0;
          slv_reg41 <= 0;
          slv_reg42 <= 0;
          slv_reg43 <= 0;
          slv_reg44 <= 0;
          slv_reg45 <= 0;
          slv_reg46 <= 0;
          slv_reg47 <= 0;
          slv_reg48 <= 0;
          slv_reg49 <= 0;
          slv_reg50 <= 0;
          slv_reg51 <= 0;
          slv_reg52 <= 0;
          slv_reg53 <= 0;
          slv_reg54 <= 0;
          slv_reg55 <= 0;
          slv_reg56 <= 0;
          slv_reg57 <= 0;
          slv_reg58 <= 0;
          slv_reg59 <= 0;
          slv_reg60 <= 0;
          slv_reg61 <= 0;
          slv_reg62 <= 0;
          slv_reg63 <= 0;
        end 
      else if (i_tx_data_vld)
        begin    
          case (i_tx_addr)
            6'h00   : slv_reg0     <= i_tx_data;
            6'h01   : slv_reg1     <= i_tx_data;
            6'h02   : slv_reg2     <= i_tx_data;
            6'h03   : slv_reg3     <= i_tx_data;
            6'h04   : slv_reg4     <= i_tx_data;
            6'h05   : slv_reg5     <= i_tx_data;
            6'h06   : slv_reg6     <= i_tx_data;
            6'h07   : slv_reg7     <= i_tx_data;
            6'h08   : slv_reg8     <= i_tx_data;
            6'h09   : slv_reg9      <= i_tx_data;
            6'h0A   : slv_reg10     <= i_tx_data;
            6'h0B   : slv_reg11     <= i_tx_data;
            6'h0C   : slv_reg12     <= i_tx_data;
            6'h0D   : slv_reg13     <= i_tx_data;
            6'h0E   : slv_reg14     <= i_tx_data;
            6'h0F   : slv_reg15     <= i_tx_data;
            6'h10   : slv_reg16     <= i_tx_data;
            6'h11   : slv_reg17     <= i_tx_data;
            6'h12   : slv_reg18     <= i_tx_data;
            6'h13   : slv_reg19     <= i_tx_data;
            6'h14   : slv_reg20     <= i_tx_data;
            6'h15   : slv_reg21     <= i_tx_data;
            6'h16   : slv_reg22     <= i_tx_data;
            6'h17   : slv_reg23     <= i_tx_data;
            6'h18   : slv_reg24     <= i_tx_data;
            6'h19   : slv_reg25     <= i_tx_data;
            6'h1A   : slv_reg26     <= i_tx_data;
            6'h1B   : slv_reg27     <= i_tx_data;
            6'h1C   : slv_reg28     <= i_tx_data;
            6'h1D   : slv_reg29     <= i_tx_data;
            6'h1E   : slv_reg30     <= i_tx_data;
            6'h1F   : slv_reg31     <= i_tx_data;
            6'h20   : slv_reg32     <= i_tx_data;
            6'h21   : slv_reg33     <= i_tx_data;
            6'h22   : slv_reg34     <= i_tx_data;
            6'h23   : slv_reg35     <= i_tx_data;
            6'h24   : slv_reg36     <= i_tx_data;
            6'h25   : slv_reg37     <= i_tx_data;
            6'h26   : slv_reg38     <= i_tx_data;
            6'h27   : slv_reg39     <= i_tx_data;
            6'h28   : slv_reg40     <= i_tx_data;
            6'h29   : slv_reg41     <= i_tx_data;
            6'h2A   : slv_reg42     <= i_tx_data;
            6'h2B   : slv_reg43     <= i_tx_data;
            6'h2C   : slv_reg44     <= i_tx_data;
            6'h2D   : slv_reg45     <= i_tx_data;
            6'h2E   : slv_reg46     <= i_tx_data;
            6'h2F   : slv_reg47     <= i_tx_data;
            6'h30   : slv_reg48     <= i_tx_data;
            6'h31   : slv_reg49     <= i_tx_data;
            6'h32   : slv_reg50     <= i_tx_data;
            6'h33   : slv_reg51     <= i_tx_data;
            6'h34   : slv_reg52     <= i_tx_data;
            6'h35   : slv_reg53     <= i_tx_data;
            6'h36   : slv_reg54     <= i_tx_data;
            6'h37   : slv_reg55     <= i_tx_data;
            6'h38   : slv_reg56     <= i_tx_data;
            6'h39   : slv_reg57     <= i_tx_data;
            6'h3A   : slv_reg58     <= i_tx_data;
            6'h3B   : slv_reg59     <= i_tx_data;
            6'h3C   : slv_reg60     <= i_tx_data;
            6'h3D   : slv_reg61     <= i_tx_data;
            6'h3E   : slv_reg62     <= i_tx_data;
            6'h3F   : slv_reg63     <= i_tx_data;
            default : begin
                slv_reg0    <= slv_reg0    ;
                slv_reg1    <= slv_reg1    ;
                slv_reg2    <= slv_reg2    ;
                slv_reg3    <= slv_reg3    ;
                slv_reg4    <= slv_reg4    ;
                slv_reg5    <= slv_reg5    ;
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