這次設計一個通用的多位元組SPI介面模塊，特點如下： 可以設置為1-128位元組的SPI通信模塊 可以修改CPOL、CPHA來進行不同的通信模式 可以設置輸出的時鐘 狀態轉移圖和思路與多位元組串口發送模塊一樣，這裡就不給出了，具體可看該隨筆。 一、模塊代碼 1、需要的模塊 通用8位SPI介面模塊 `tim ...
這次設計一個通用的多位元組SPI介面模塊，特點如下：
- 可以設置為1-128位元組的SPI通信模塊
- 可以修改CPOL、CPHA來進行不同的通信模式
- 可以設置輸出的時鐘
狀態轉移圖和思路與多位元組串口發送模塊一樣，這裡就不給出了，具體可看該隨筆。
一、模塊代碼
1、需要的模塊
通用8位SPI介面模塊
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Lclone
//
// Create Date: 2023/01/23 00:56:52
// Design Name: SPI_Interface
// Module Name: SPI_Interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// SPI介面模塊
// 可修改分頻參數來生成目標頻率，最低分頻繫數為2；
// 可以置位CPOL、CPHA可以來設置通信模式；
// 本模塊只有1位，但是可以簡單修改位寬來設置多位片選信號
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_Interface
# (
parameter Value_divide = 2)//分頻繫數（最低為2）
(
//-----------------內部介面------------------
input Clk, //時鐘
input Rst_n, //複位信號
input CPOL, //時鐘極性
input CPHA, //時鐘相位
input CS_input, //片選信號
input Send_en, //發送使能
input [7:0] Data_send, //待發送數據
output reg Read_en, //接收數據讀使能
output reg [7:0] Data_recive, //接收到的數據
//------------------外部介面------------------
output reg Spi_clk, //輸出時鐘端
output reg Spi_mosi, //主輸出從接收端
input Spi_miso, //主接收從輸出端
output Cs_output //片選信號輸出
);
reg act_flag; //活動狀態寄存器
reg [9:0] cnt_divide; //分頻計數器
reg [7:0] Data_send_reg; //帶發送數據寄存器
reg [4:0] cnt_pulse; //脈衝計數器
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
act_flag <= 0;
else if(Send_en == 1)
act_flag <= 1;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1 & cnt_pulse == 16)
act_flag <= 0;
else
act_flag <= act_flag;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
Read_en <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1 & cnt_pulse == 16)
Read_en <= 1;
else
Read_en <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
Data_send_reg <= 0;
else if(Send_en == 1)
Data_send_reg <= Data_send;
else
cnt_divide <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
cnt_divide <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1)
cnt_divide <= 0;
else if(act_flag == 1)
cnt_divide <= cnt_divide + 1'b1;
else
cnt_divide <= 0;
end
always @(posedge Clk or negedge Rst_n) begin//生成目標時鐘兩倍頻率的的cnt_pulse
if(Rst_n == 0)
cnt_pulse <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1 & cnt_pulse == 16)
cnt_pulse <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1)
cnt_pulse <= cnt_pulse + 1'b1;
else if(act_flag == 1)
cnt_pulse <= cnt_pulse;
else
cnt_pulse <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
begin
if(CPOL == 1)
begin
Spi_clk <= 1;
Spi_mosi <= 1;
Data_recive <= 0;
end
else
begin
Spi_clk <= 0;
Spi_mosi <= 1;
Data_recive <= 0;
end
end
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1)
begin
if(CPHA == 0)
case(cnt_pulse)
0:begin
Spi_clk <= Spi_clk;
Spi_mosi <= Data_send_reg[7];
Data_recive <= Data_recive;
end
1:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[7] <= Spi_miso;
end
2:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[6];
Data_recive <= Data_recive;
end
3:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[6] <= Spi_miso;
end
4:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[5];
Data_recive <= Data_recive;
end
5:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[5] <= Spi_miso;
end
6:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[4];
Data_recive <= Data_recive;
end
7:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[4] <= Spi_miso;
end
8:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[3];
Data_recive <= Data_recive;
end
9:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[3] <= Spi_miso;
end
10:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[2];
Data_recive <= Data_recive;
end
11:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[2] <= Spi_miso;
end
12:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[1];
Data_recive <= Data_recive;
end
13:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[1] <= Spi_miso;
end
14:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[0];
Data_recive <= Data_recive;
end
15:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[0] <= Spi_miso;
end
16:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= 1;
Data_recive <= Data_recive;
end
default:;
endcase
else
case(cnt_pulse)
0:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[7];
Data_recive <= Data_recive;
end
1:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[7] <= Spi_miso;
end
2:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[6];
Data_recive <= Data_recive;
end
3:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[6] <= Spi_miso;
end
4:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[5];
Data_recive <= Data_recive;
end
5:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[5] <= Spi_miso;
end
6:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[4];
Data_recive <= Data_recive;
end
7:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[4] <= Spi_miso;
end
8:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[3];
Data_recive <= Data_recive;
end
9:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[3] <= Spi_miso;
end
10:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[2];
Data_recive <= Data_recive;
end
11:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[2] <= Spi_miso;
end
12:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[1];
Data_recive <= Data_recive;
end
13:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[1] <= Spi_miso;
end
14:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[0];
Data_recive <= Data_recive;
end
15:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[0] <= Spi_miso;
end
16:begin
Spi_clk <= Spi_clk;
Spi_mosi <= 1;
Data_recive <= Data_recive;
end
default:;
endcase
end
end
assign Cs_output = CS_input;
endmodule
2、設計的模塊
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: GDUT
// Engineer: Lclone
//
// Create Date: 2023/01/23 22:12:11
// Design Name: SPI_Bytes
// Module Name: SPI_Bytes
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// - 可以設置位1-128位元組的SPI通信模塊
// - 可以修改CPOL、CPHA來進行不同的通信模式
// - 可以設置輸出的時鐘
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_Bytes
# (
parameter Data_Width = 16, //數據位寬
parameter ROUNDS = Data_Width/8) //傳輸輪數（例化時不需要設置）
(
//-----------------內部介面--------------------
input Clk, //時鐘信號
input Rst_n, //複位信號
input [Data_Width-1:0] Send_Bytes_Data, //發送的多位元組數據
input Bytes_Send_en, //多位元組發送使能
output reg [Data_Width-1:0] Recive_Bytes_Data, //接收的多位元組數據
output reg Bytes_Read_en, //多位元組讀使能
input Cs_input, //片選信號輸入
//-----------------外部介面--------------------
output Spi_mosi, //主輸出從輸入
input Spi_miso, //主輸入從輸出
output Spi_clk, //輸出時鐘
output Cs_output //片選信號輸出
);
reg send_en; //發送使能
wire read_en; //讀使能
reg [7:0] data_send; //待發送數據
reg [Data_Width-1:0] Send_Bytes_Data_reg; //多位元組數據寄存器
wire[7:0] data_recive; //接收的數據
reg [9:0] round; //發送次數（修改該位寬可改變最大發送數據位寬）
reg [1:0] state; //狀態寄存器
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
round <= 0;
else if(round == ROUNDS)
round <= 0;
else if(read_en == 1)
round <= round + 1'b1;
else
round <= round;
end
always @(posedge Clk or negedge Rst_n) begin//狀態機
if(Rst_n == 0)
begin
state <= 0;
Bytes_Read_en <= 0;
data_send <= 0;
Send_Bytes_Data_reg <= 0;
send_en <= 0;
Recive_Bytes_Data <= 0;
end
else case(state)
0://空閑狀態
begin
Bytes_Read_en <= 0;
if(Bytes_Send_en == 1)
begin
state <= 1;
Send_Bytes_Data_reg <= Send_Bytes_Data;
end
else
state <= 0;
end
1://發送狀態
begin
send_en <= 0;
if(round == ROUNDS)
begin
state <= 0;
Bytes_Read_en <= 1;
Recive_Bytes_Data[7:0] <= data_recive;//由於發送和接收的時序略有不同，這裡給接收做個補償。
end
else
begin
state <= 2;
send_en <= 1;
data_send <= Send_Bytes_Data_reg[Data_Width-1:Data_Width-8];//發送高位
Recive_Bytes_Data[7:0] <= data_recive;//把接收到的數據放在低位
end
end
2://數據移位
begin
send_en <= 0;
if(read_en == 1)
begin
Send_Bytes_Data_reg <= Send_Bytes_Data_reg << 8;//高位刷新
Recive_Bytes_Data <= Recive_Bytes_Data << 8;//把低位的數據移到高位
state <= 1;
end
else
state <= 2;
end
default:;
endcase
end
SPI_Interface
# (
.Value_divide (4)) //分頻繫數
SPI_SPI_Interface_inst
(
//-----------------內部介面------------------
.Clk (Clk), //時鐘信號
.Rst_n (Rst_n), //複位信號
.CPOL (1),
.CPHA (0),
.CS_input (1), //片選輸入
.Send_en (send_en), //發送使能
.Data_send (data_send), //待發送數據
.Read_en (read_en), //讀使能
.Data_recive (data_recive), //接收的數據
//------------------外部介面------------------
.Spi_clk (Spi_clk), //輸出時鐘
.Spi_mosi (Spi_mosi), //主輸出從輸入
.Spi_miso (Spi_miso), //主輸入從輸出
.Cs_output (Cs_output) //片選輸出
);
endmodule
二、模擬
1、模擬激勵
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/01/26 16:00:48
// Design Name:
// Module Name: SPI_Bytes_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_Bytes_tb();
reg clk_50m;
initial clk_50m <= 1;
always #10 clk_50m <= ~clk_50m;
reg rst_n;
initial begin
rst_n <= 0;
#200
rst_n <= 1;
end
reg Bytes_Send_en;
reg [31:0] Send_Bytes_Data;
wire Bytes_Read_en;
wire [31:0] Recive_Bytes_Data;
wire Spi_clk;
wire Spi_mosi;
wire Spi_miso;
wire Cs_output;
SPI_Bytes
# (
.Data_Width (32))//數據位寬為32位
SPI_Bytes_inst
(
//-----------------內部介面--------------------
.Clk (clk_50m),
.Rst_n (rst_n),
.Send_Bytes_Data (Send_Bytes_Data),
.Bytes_Send_en (Bytes_Send_en),
.Recive_Bytes_Data (Recive_Bytes_Data),
.Bytes_Read_en (Bytes_Read_en),
.Cs_input (1'b1),
//-----------------外部介面--------------------
.Spi_mosi (Spi_mosi),
.Spi_miso (Spi_miso),
.Spi_clk (Spi_clk),
.Cs_output (Cs_output)
);
assign Spi_miso = Spi_mosi;
initial begin
Bytes_Send_en <= 0;
Send_Bytes_Data <= 0;
#400;
Bytes_Send_en <= 1;
Send_Bytes_Data <= 32'h89abcdef;
#20
Bytes_Send_en <= 0;
#4000;
Bytes_Send_en <= 1;
Send_Bytes_Data <= 32'h12345678;
#20
Bytes_Send_en <= 0;
end
endmodule
2、模擬結果
模擬結果：兩次多位元組發送都能正確的發送和接收數據，且能正確的生成Bytes_Read_en信號。模塊模擬驗證可行。
