這次設計一個可以接收多位元組（通過修改例化時的位寬實現）的串口接收模塊。 當接收到9個位元組的數據，但是我們只需要8個位元組的數據時候，我們需要的是前八位的數據還是後八位的數據我們無法確定。 所以我們需要設定一種傳輸協議，這種協議我們可以自定義規則。我們就設定首碼為8'h55+8'hA5，尾碼為8'hF0 ...
這次設計一個可以接收多位元組（通過修改例化時的位寬實現）的串口接收模塊。
當接收到9個位元組的數據，但是我們只需要8個位元組的數據時候，我們需要的是前八位的數據還是後八位的數據我們無法確定。
所以我們需要設定一種傳輸協議，這種協議我們可以自定義規則。我們就設定首碼為8'h55+8'hA5，尾碼為8'hF0的一串數據即為我們需要的數據。
1、狀態機的設定
2、需要的模塊
(1) 8位串口接收模塊
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Lclone
//
// Create Date: 2022/12/16 15:37:44
// Design Name: uart_byte_rx
// Module Name: uart_byte_rx
// Project Name: uart_byte_rx
// Target Devices:
// Tool Versions:
// Description: 8位串口接收模塊
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_byte_rx
# (
parameter RX_BAUD = 9600, //波特率
parameter CLK_FQC = 50_000_000, //模塊時鐘頻率
parameter BAUD_CNT = CLK_FQC/RX_BAUD) //模塊每波特需要計數的次數（設置此埠方便模擬用）
(
input Clk, //時鐘頻率介面
input Rst_n, //複位介面
input Uart_rx, //串口接收介面
output reg [7:0] Data, //接收到的數據介面
output reg Rx_done //接收完成信號
);
reg uart_rx_r; //延一拍
reg uart_rx_rr; //延兩拍
reg receiv_begin; //接收開始信號
reg receiv_flag; //接收狀態信號
reg [ 3:0] state; //狀態機寄存器
reg [15:0] baud_cnt; //波及計數器
reg [ 3:0] sampel_cnt; //採樣計數器
reg sampel_en; //採樣使能
reg sampel_ref; //樣本寄存器
reg [ 3:0] acc; //累加寄存器
reg [ 3:0] bit_cnt; //數據位寄存器
always @(posedge Clk) begin //延兩拍為下降沿捕獲
uart_rx_r <= Uart_rx;
uart_rx_rr <= uart_rx_r;
end
always @(posedge Clk or negedge Rst_n) begin //接收信號發生
if(Rst_n == 0)
receiv_begin <= 0;
else if(state == 0 & uart_rx_rr & ~uart_rx_r)
receiv_begin <= 1'b1;
else
receiv_begin <= 0;
end
always @(posedge Clk or negedge Rst_n) begin //狀態機
if(Rst_n == 0) begin
state <= 0;
sampel_ref <= 8'b0;
acc <= 8'b0;
Data <= 8'b0;
end
else case(state)
0: //空閑狀態
if(receiv_begin == 1)
state <= 3'd1;
else
state <= 0;
1: begin //抽樣狀態
if(sampel_en == 1) begin
sampel_ref <= Uart_rx;
state <= 3'd2;
end
else
state <= 3'b1;
end
2: begin //數據判斷狀態
acc <= acc + sampel_ref;
if(sampel_cnt == 7) begin
if(acc >= 4)
begin Data[7] <= 1'b1; state <= 3'd3;acc <= 8'b0; end
else
begin Data[7] <= 0; state <= 3'd3;acc <= 8'b0; end
end
else
state <= 3'd1;
end
3: begin //數據移位狀態
if(bit_cnt < 8) begin
Data <= Data >> 1;
state <= 3'd1;
end
else
state <= 0;
end
default:;
endcase
end
always @(posedge Clk or negedge Rst_n) begin //接收進行標誌
if(Rst_n == 0)
receiv_flag <= 0;
else if(receiv_begin == 1)
receiv_flag <= 1'b1;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8) //這裡設置為記到BAUD_CNT/9*8是為了讓Rx_done信號提前一點產生，避免因為Rx_done出現過晚，導致錯過下一個起始位的下降沿。後面和其相同的條件判斷，也是因為相同原因設置的。
receiv_flag <= 1'b0;
end
always @(posedge Clk or negedge Rst_n) begin //波特計數
if(Rst_n == 0)
baud_cnt <= 0;
else if(receiv_flag == 1) begin
if(baud_cnt == BAUD_CNT - 1)
baud_cnt <= 0;
else
baud_cnt <= baud_cnt + 1'b1;
end
else
baud_cnt <= 0;
end
always @(posedge Clk or negedge Rst_n) begin //採樣計數
if(Rst_n == 0) begin
sampel_cnt <= 0;
sampel_en <= 0;
end
else if(receiv_flag == 1) begin
case(baud_cnt)
BAUD_CNT/9*1-1 : begin sampel_cnt <= 0; sampel_en <=1; end
BAUD_CNT/9*2-1 : begin sampel_cnt <= 1; sampel_en <=1; end
BAUD_CNT/9*3-1 : begin sampel_cnt <= 2; sampel_en <=1; end
BAUD_CNT/9*4-1 : begin sampel_cnt <= 3; sampel_en <=1; end
BAUD_CNT/9*5-1 : begin sampel_cnt <= 4; sampel_en <=1; end
BAUD_CNT/9*6-1 : begin sampel_cnt <= 5; sampel_en <=1; end
BAUD_CNT/9*7-1 : begin sampel_cnt <= 6; sampel_en <=1; end
BAUD_CNT/9*8-1 : begin sampel_cnt <= 7; sampel_en <=1; end
BAUD_CNT/9*9-1 : sampel_cnt <= 0;
default:sampel_en <=0;
endcase
end
end
always @(posedge Clk or negedge Rst_n) begin //數據位計數
if(Rst_n == 0)
bit_cnt <= 0;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
bit_cnt <= 0;
else if(baud_cnt == BAUD_CNT - 1)
bit_cnt <= bit_cnt + 1'b1;
end
always @(posedge Clk or negedge Rst_n) begin //接收完成信號產生
if(Rst_n == 0)
Rx_done <= 0;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
Rx_done <= 1'b1;
else
Rx_done <= 0;
end
endmodule
3、設計的模塊代碼
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/12/25 00:26:10
// Design Name:
// Module Name: uart_bytes_rx
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_bytes_rx
#( parameter DATA_WIDTH = 64,//數據位寬
parameter PREFIX1 = 8'h55,//首碼1
parameter PREFIX2 = 8'hA5,//首碼2
parameter ENDINGS = 8'hF0)//尾碼
(
input Clk, //時鐘信號
input Rst_n, //複位信號
input Uart_rx, //串口接收埠
output reg[DATA_WIDTH-1-8*3:0] Bytes_data, //多位元組數據埠
output reg Bytes_Rx_done //多位元組接收完成
);
reg [2:0] state; //狀態機寄存器
reg [DATA_WIDTH-1:0] bytes_data_reg; //多位元組數據接收寄存器
wire [7:0] rx_data_reg; //8位數據接收寄存器
wire Rx_done; //8位數據接收完成信號
uart_byte_rx
# (
.RX_BAUD (115200), //波特率
.CLK_FQC (50_000_000)) //時鐘頻率
uart_byte_rx_inst
(
.Clk (Clk), //時鐘
.Rst_n (Rst_n), //複位
.Uart_rx (Uart_rx), //串口接收埠
.Data (rx_data_reg), //8位數據埠
.Rx_done (Rx_done) //8位數據接收完成
);
always @(posedge Clk or negedge Rst_n) begin//狀態機
if(Rst_n == 0) begin
state <= 0;
bytes_data_reg <= 0;
Bytes_Rx_done <= 0;
Bytes_data <= 0;
end else case(state)
0:begin
if(Rx_done) begin
bytes_data_reg[DATA_WIDTH-1:DATA_WIDTH-1-7] <= rx_data_reg;//數據裝載
state <= 3'd1;
end else begin
state <= 0;
Bytes_Rx_done <= 0;
end
end
1:begin
if(bytes_data_reg[DATA_WIDTH-1:DATA_WIDTH-1-7] == ENDINGS
&& bytes_data_reg[15:8] ==PREFIX2
&& bytes_data_reg[7:0] ==PREFIX1)//數據協議判斷
begin
Bytes_data <= bytes_data_reg[DATA_WIDTH-1-8:16];
state <= 1'b0;
Bytes_Rx_done <= 1'b1;
bytes_data_reg <= 0;
end
else
state <= 3'd2;
end
2:begin
bytes_data_reg <= bytes_data_reg >> 8;//數據移位
state <= 0;
end
endcase
end
endmodule
4、模擬驗證
(1)模擬激勵文件
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/12/26 16:14:35
// Design Name:
// Module Name: uart_bytes_rx_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_bytes_rx_tb();
reg CLK_50M;
reg RST_N;
wire [39:0] Bytes_data;
reg Uart_rx;
wire Bytes_Rx_done;
uart_bytes_rx
# (
.DATA_WIDTH (64))
uart_bytes_rx_inst
(
.Clk (CLK_50M),
.Rst_n (RST_N),
.Uart_rx (Uart_rx),
.Bytes_data (Bytes_data),
.Bytes_Rx_done (Bytes_Rx_done)
);
defparam uart_bytes_rx_inst.uart_byte_rx_inst.BAUD_CNT = 50;
always #10 CLK_50M <= ~CLK_50M;
initial begin
CLK_50M <= 1'b0;
RST_N <= 1'b0;
Uart_rx <= 1'b1;
#100
RST_N <= 1'b1;
#20
data_deliver(8'h55);
#100
data_deliver(8'hA5);
#100
data_deliver(8'h01);
#100
data_deliver(8'h23);
#100
data_deliver(8'h45);
#100
data_deliver(8'h67);
#100
data_deliver(8'h89);
#100
data_deliver(8'hf0);
#100
$stop;
end
task data_deliver;
input [7:0] test_data;
begin
Uart_rx <= 1'b0;
#1000
Uart_rx <= test_data[0];
#1000
Uart_rx <= test_data[1];
#1000
Uart_rx <= test_data[2];
#1000
Uart_rx <= test_data[3];
#1000
Uart_rx <= test_data[4];
#1000
Uart_rx <= test_data[5];
#1000
Uart_rx <= test_data[6];
#1000
Uart_rx <= test_data[7];
#1000
Uart_rx <= 1'b1;
#1000;
end
endtask
endmodule
(2)模擬結果
5、應用實例
我們把它應用為一個通過接收電腦串口發送的數據從而改變8位LED每位是否閃爍和閃爍的周期的程式。
其中有效的數據段中，第1個位元組的數據控制LED燈是否閃爍，第2、3位元組的數據控制閃爍的周期。
周期的計算公式為： T = 寫入的值 X 10us X 2
top.v
`timescale 1ns / 1ps
module Top(
input Sclk,
input Rst_n,
input Uart_rx,
output [7:0] LED
);
wire [23:0] Bytes_data;
wire Bytes_Rx_done;
uart_bytes_rx
# ( .DATA_WIDTH (48),
.PREFIX1 (8'h55),
.PREFIX2 (8'hA5),
.ENDINGS (8'hF0))
uart_bytes_rx_inst
(
.Clk (Sclk),
.Rst_n (Rst_n),
.Uart_rx (Uart_rx),
.Bytes_data (Bytes_data),
.Bytes_Rx_done (Bytes_Rx_done)
);
LED_6 LED_6_inst(
.SCLK (Sclk),
.RST_N (Rst_n),
.CTRL_IN (Bytes_data[7:0]),
.Time (Bytes_data[23:8]),
.LED (LED)
);
endmodule
uart_bytes_rx.v
`timescale 1ns / 1ps
module uart_bytes_rx
#( parameter DATA_WIDTH = 64,//數據位寬
parameter PREFIX1 = 8'h55,//首碼1
parameter PREFIX2 = 8'hA5,//首碼2
parameter ENDINGS = 8'hF0)//尾碼
(
input Clk, //時鐘信號
input Rst_n, //複位信號
input Uart_rx, //串口接收埠
output reg[DATA_WIDTH-1-8*3:0] Bytes_data, //多位元組數據埠
output reg Bytes_Rx_done //多位元組接收完成
);
reg [2:0] state; //狀態機寄存器
reg [DATA_WIDTH-1:0] bytes_data_reg; //多位元組數據接收寄存器
wire [7:0] rx_data_reg; //8位數據接收寄存器
wire Rx_done; //8位數據接收完成信號
uart_byte_rx
# (
.RX_BAUD (115200), //波特率
.CLK_FQC (50_000_000)) //時鐘頻率
uart_byte_rx_inst
(
.Clk (Clk), //時鐘
.Rst_n (Rst_n), //複位
.Uart_rx (Uart_rx), //串口接收埠
.Data (rx_data_reg), //8位數據埠
.Rx_done (Rx_done) //8位數據接收完成
);
always @(posedge Clk or negedge Rst_n) begin//狀態機
if(Rst_n == 0) begin
state <= 0;
bytes_data_reg <= 0;
Bytes_Rx_done <= 0;
Bytes_data <= 0;
end else case(state)
0:begin
if(Rx_done) begin
bytes_data_reg[DATA_WIDTH-1:DATA_WIDTH-1-7] <= rx_data_reg;//數據裝載
state <= 3'd1;
end else begin
state <= 0;
Bytes_Rx_done <= 0;
end
end
1:begin
if(bytes_data_reg[DATA_WIDTH-1:DATA_WIDTH-1-7] == ENDINGS
&& bytes_data_reg[15:8] ==PREFIX2
&& bytes_data_reg[7:0] ==PREFIX1)//數據協議判斷
begin
Bytes_data <= bytes_data_reg[DATA_WIDTH-1-8:16];
state <= 1'b0;
Bytes_Rx_done <= 1'b1;
bytes_data_reg <= 0;
end
else
state <= 3'd2;
end
2:begin
bytes_data_reg <= bytes_data_reg >> 8;//數據移位
state <= 0;
end
endcase
end
endmodule
uart_byte_rx.v
`timescale 1ns / 1ps
module uart_byte_rx
# (
parameter RX_BAUD = 9600,
parameter CLK_FQC = 50_000_000,
parameter BAUD_CNT = CLK_FQC/RX_BAUD)
(
input Clk,
input Rst_n,
input Uart_rx,
output reg [7:0] Data,
output reg Rx_done
);
reg uart_rx_r;
reg uart_rx_rr;
reg receiv_begin;
reg receiv_flag;
reg [ 3:0] state;
reg [15:0] baud_cnt;
reg [ 3:0] sampel_cnt;
reg sampel_en;
reg sampel_ref;
reg [ 3:0] acc;
reg [ 3:0] bit_cnt;
always @(posedge Clk) begin
uart_rx_r <= Uart_rx;
uart_rx_rr <= uart_rx_r;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
receiv_begin <= 0;
else if(state == 0 & uart_rx_rr & ~uart_rx_r)
receiv_begin <= 1'b1;
else
receiv_begin <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0) begin
state <= 0;
sampel_ref <= 8'b0;
acc <= 8'b0;
Data <= 8'b0;
end
else case(state)
0:
if(receiv_begin == 1)
state <= 3'd1;
else
state <= 0;
1: begin
if(sampel_en == 1) begin
sampel_ref <= Uart_rx;
state <= 3'd2;
end
else
state <= 3'b1;
end
2: begin
acc <= acc + sampel_ref;
if(sampel_cnt == 7) begin
if(acc >= 4)
begin Data[7] <= 1'b1; state <= 3'd3;acc <= 8'b0; end
else
begin Data[7] <= 0; state <= 3'd3;acc <= 8'b0; end
end
else
state <= 3'd1;
end
3: begin
if(bit_cnt < 8) begin
Data <= Data >> 1;
state <= 3'd1;
end
else
state <= 0;
end
default:;
endcase
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
receiv_flag <= 0;
else if(receiv_begin == 1)
receiv_flag <= 1'b1;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
receiv_flag <= 1'b0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
baud_cnt <= 0;
else if(receiv_flag == 1) begin
if(baud_cnt == BAUD_CNT - 1)
baud_cnt <= 0;
else
baud_cnt <= baud_cnt + 1'b1;
end
else
baud_cnt <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0) begin
sampel_cnt <= 0;
sampel_en <= 0;
end
else if(receiv_flag == 1) begin
case(baud_cnt)
BAUD_CNT/9*1-1 : begin sampel_cnt <= 0; sampel_en <=1; end
BAUD_CNT/9*2-1 : begin sampel_cnt <= 1; sampel_en <=1; end
BAUD_CNT/9*3-1 : begin sampel_cnt <= 2; sampel_en <=1; end
BAUD_CNT/9*4-1 : begin sampel_cnt <= 3; sampel_en <=1; end
BAUD_CNT/9*5-1 : begin sampel_cnt <= 4; sampel_en <=1; end
BAUD_CNT/9*6-1 : begin sampel_cnt <= 5; sampel_en <=1; end
BAUD_CNT/9*7-1 : begin sampel_cnt <= 6; sampel_en <=1; end
BAUD_CNT/9*8-1 : begin sampel_cnt <= 7; sampel_en <=1; end
BAUD_CNT/9*9-1 : sampel_cnt <= 0;
default:sampel_en <=0;
endcase
end
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
bit_cnt <= 0;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
bit_cnt <= 0;
else if(baud_cnt == BAUD_CNT - 1)
bit_cnt <= bit_cnt + 1'b1;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
Rx_done <= 0;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
Rx_done <= 1'b1;
else
Rx_done <= 0;
end
endmodule
LED_6.v
`timescale 1ns / 1ps
module LED_6(
input SCLK,
input RST_N,
input [ 7:0] CTRL_IN,
input [15:0] Time,
output reg [ 7:0] LED
);
parameter DELAY_10US = 500;
parameter COUNT_10MS = 1000;
reg [8:0] count_10us;
reg [15:0] count_time;
reg led_flag;
always @(posedge SCLK or negedge RST_N) begin
if(RST_N == 0)
count_10us <= 0;
else if(count_10us == DELAY_10US - 1)
count_10us <= 0;
else
count_10us <= count_10us + 1'b1;
end
always @(posedge SCLK or negedge RST_N) begin
if(RST_N == 0)
count_time <= 0;
else if(count_time == Time - 1)
count_time <= 0;
else if(count_10us == DELAY_10US - 1)
count_time <= count_time + 1'b1;
end
always @(posedge SCLK or negedge RST_N) begin
if(RST_N == 0)
led_flag <= 0;
else if(count_time == COUNT_10MS - 1)
led_flag <= ~led_flag;
end
always @(posedge SCLK or negedge RST_N) begin
if(RST_N == 0)
LED <= 0;
else if(count_time == COUNT_10MS - 1 & led_flag == 1)
LED <= CTRL_IN;
else if(count_time == COUNT_10MS - 1 & led_flag == 0)
LED <= 0;
end
endmodule
上板效果
這裡電腦的串口收到00數據是因為沒有設置開發板的串口TX埠，導致其懸空了，受到了干擾所導致的，可以將其設置為高電平輸出，以解決該問題。
可見的LED燈按照設定方式進行閃爍，可見此設計成功。
（數位管亮是因為控制該數位管的移位寄存器的問題）
