Verilog HDL交通燈的實現

在家實在閑的沒事兒乾，翻出來了大三上學期的EDA課的小實驗，也就是設計一個二愣子交通燈啦，只會自己按設定好的時間閃,紅燈、綠燈，黃燈和轉向燈；

• 各燈顯示時長：哎呀~ 懶得寫了，後面程式里都有。
• 晶元：FPGA、Cylone IV E 系列的 EP4CE6E22C8，144引腳。
• 外置時鐘：1Hz

以下是這個小實驗的完整的程式：

module	traffic(
			input clk,
			output reg r1,
			output reg y1,
			output reg g1,
			output reg b1,
			output reg r2,
			output reg y2,
			output reg g2,
			output reg b2
			);
		parameter yellow_time = 5;
		parameter green_time  = 20;
		parameter blue_time = 10;
		reg [2:0] state;

		always @(posedge clk)
			case (state)
				0:		/*南北綠，東西紅*/
					begin
						r1 <= 1'b0;
						y1 <= 1'b0;
						g1 <= 1'b1;
						b1 <= 1'b0;
						r2 <= 1'b1;
						y2 <= 1'b0;
						g2 <= 1'b0;
					   b2 <= 1'b0;
					end
				1:		/*南北黃，東西紅*/
					begin
						r1 <= 1'b0;
						y1 <= 1'b1;
						g1 <= 1'b0;
						b1 <= 1'b0;
						r2 <= 1'b1;
						y2 <= 1'b0;
						g2 <= 1'b0;
						b2 <= 1'b0;
					end
				2:		/*南北左轉，東西紅*/
					begin
						r1 <= 1'b0;
						y1 <= 1'b0;
						g1 <= 1'b0;
						b1 <= 1'b1;
						r2 <= 1'b1;
						y2 <= 1'b0;
						g2 <= 1'b0;
						b2 <= 1'b0;
					end
				3:	/*南北紅，東西綠*/
					begin
						r1 <= 1'b1;
						y1 <= 1'b0;
						g1 <= 1'b0;
						b1 <= 1'b0;
						r2 <= 1'b0;
						y2 <= 1'b0;
						g2 <= 1'b1;
						b2 <= 1'b0;
					end
				4:	/*南北紅，東西黃*/
					begin
						r1 <= 1'b1;
						y1 <= 1'b0;
						g1 <= 1'b0;
						b1 <= 1'b0;
						
						r2 <= 1'b0;
						y2 <= 1'b1;
						g2 <= 1'b0;
						b2 <= 1'b0;
					end
				
				
			default:	/*南北紅，東西左轉*/
				begin
					r1 <= 1'b1;
					y1 <= 1'b0;
					g1 <= 1'b0;
					b1 <= 1'b0;
					r2 <= 1'b0;
					y2 <= 1'b0;
					g2 <= 1'b0;
					b2 <= 1'b1;
				end
			endcase
		
		always @(posedge clk)
			begin
				reg [4:0] count;
				begin
					if(count == 0)
						begin
							if(state == 5)
								state <= 0;
							else 
								state <= state +1;
							case	(state)
								0:
									count = yellow_time;
								1:
									count = blue_time;
								2:
									count =  green_time;
								3:
									count = yellow_time;
								4:
									count = blue_time;
								default:
									count = green_time;
							endcase
						end
					else
						count = count - 1;				
				end 			
			end 
endmodule

這個是引腳配置，書上都有噠，就是順序老是配反，搞得我改了好幾遍（其實本人很細心得啦QAQ）。

這個是最後的那個原理圖