本次設計一個八位的SPI的介面模塊，可以修改輸出的頻率，也可以通過修改參數來設置通信模式。 本模塊是設定生成一個目標輸出頻率的二倍的計數器，然後通關計數的值來輸出響應的信號，從而進行SPI通信。 本模塊既可以發送數據也可以接收數據，給Send_en信號使開始發送數據，在接收到8位數據後會生成Read ...
本次設計一個八位的SPI的介面模塊，可以修改輸出的頻率，也可以通過修改參數來設置通信模式。
本模塊是設定生成一個目標輸出頻率的二倍的計數器，然後通關計數的值來輸出響應的信號，從而進行SPI通信。
本模塊既可以發送數據也可以接收數據，給Send_en信號使開始發送數據，在接收到8位數據後會生成Read_en信號。
片選信號只設定了1位，但是可以通過簡單的修改位寬來設置多位。
一、模塊代碼
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Lclone
//
// Create Date: 2023/01/23 00:56:52
// Design Name: SPI_Interface
// Module Name: SPI_Interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// SPI介面模塊
// 可修改分頻參數來生成目標頻率，最低分頻繫數為2；
// 可以置位CPOL、CPHA可以來設置通信模式；
// 本模塊只有1位，但是可以簡單修改位寬來設置多位片選信號
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_Interface
# (
parameter Value_divide = 2)//分頻繫數（最低為2）
(
//-----------------內部介面------------------
input Clk, //時鐘
input Rst_n, //複位信號
input CPOL, //時鐘極性
input CPHA, //時鐘相位
input CS_input, //片選信號
input Send_en, //發送使能
input [7:0] Data_send, //待發送數據
output reg Read_en, //接收數據讀使能
output reg [7:0] Data_recive, //接收到的數據
//------------------外部介面------------------
output reg Spi_clk, //輸出時鐘端
output reg Spi_mosi, //主輸出從接收端
input Spi_miso, //主接收從輸出端
output Cs_output //片選信號輸出
);
reg act_flag; //活動狀態寄存器
reg [9:0] cnt_divide; //分頻計數器
reg [7:0] Data_send_reg; //帶發送數據寄存器
reg [4:0] cnt_pulse; //脈衝計數器
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
act_flag <= 0;
else if(Send_en == 1)
act_flag <= 1;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1 & cnt_pulse == 16)
act_flag <= 0;
else
act_flag <= act_flag;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
Read_en <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1 & cnt_pulse == 16)
Read_en <= 1;
else
Read_en <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
Data_send_reg <= 0;
else if(Send_en == 1)
Data_send_reg <= Data_send;
else
cnt_divide <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
cnt_divide <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1)
cnt_divide <= 0;
else if(act_flag == 1)
cnt_divide <= cnt_divide + 1'b1;
else
cnt_divide <= 0;
end
always @(posedge Clk or negedge Rst_n) begin//生成目標時鐘兩倍頻率的的cnt_pulse
if(Rst_n == 0)
cnt_pulse <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1 & cnt_pulse == 16)
cnt_pulse <= 0;
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1)
cnt_pulse <= cnt_pulse + 1'b1;
else if(act_flag == 1)
cnt_pulse <= cnt_pulse;
else
cnt_pulse <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
begin
if(CPOL == 1)
begin
Spi_clk <= 1;
Spi_mosi <= 1;
Data_recive <= 0;
end
else
begin
Spi_clk <= 0;
Spi_mosi <= 1;
Data_recive <= 0;
end
end
else if(cnt_divide == Value_divide/2 - 1 & act_flag == 1)
begin
if(CPHA == 0)
case(cnt_pulse)
0:begin
Spi_clk <= Spi_clk;
Spi_mosi <= Data_send_reg[7];
Data_recive <= Data_recive;
end
1:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[7] <= Spi_miso;
end
2:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[6];
Data_recive <= Data_recive;
end
3:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[6] <= Spi_miso;
end
4:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[5];
Data_recive <= Data_recive;
end
5:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[5] <= Spi_miso;
end
6:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[4];
Data_recive <= Data_recive;
end
7:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[4] <= Spi_miso;
end
8:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[3];
Data_recive <= Data_recive;
end
9:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[3] <= Spi_miso;
end
10:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[2];
Data_recive <= Data_recive;
end
11:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[2] <= Spi_miso;
end
12:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[1];
Data_recive <= Data_recive;
end
13:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[1] <= Spi_miso;
end
14:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[0];
Data_recive <= Data_recive;
end
15:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[0] <= Spi_miso;
end
16:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= 1;
Data_recive <= Data_recive;
end
default:;
endcase
else
case(cnt_pulse)
0:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[7];
Data_recive <= Data_recive;
end
1:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[7] <= Spi_miso;
end
2:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[6];
Data_recive <= Data_recive;
end
3:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[6] <= Spi_miso;
end
4:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[5];
Data_recive <= Data_recive;
end
5:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[5] <= Spi_miso;
end
6:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[4];
Data_recive <= Data_recive;
end
7:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[4] <= Spi_miso;
end
8:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[3];
Data_recive <= Data_recive;
end
9:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[3] <= Spi_miso;
end
10:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[2];
Data_recive <= Data_recive;
end
11:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[2] <= Spi_miso;
end
12:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[1];
Data_recive <= Data_recive;
end
13:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[1] <= Spi_miso;
end
14:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Data_send_reg[0];
Data_recive <= Data_recive;
end
15:begin
Spi_clk <= ~Spi_clk;
Spi_mosi <= Spi_mosi;
Data_recive[0] <= Spi_miso;
end
16:begin
Spi_clk <= Spi_clk;
Spi_mosi <= 1;
Data_recive <= Data_recive;
end
default:;
endcase
end
end
assign Cs_output = CS_input;
endmodule
二、模擬
1、模擬激勵
`timescale 1ns / 1ps
module SPI_tb();
reg clk_50m;
initial clk_50m <= 1;
always #10 clk_50m <= ~clk_50m;
reg rst_n;
initial begin
rst_n <= 0;
#200
rst_n <= 1;
end
reg Send_en;
reg [7:0]Data_send;
wire Read_en;
wire [7:0]Data_recive;
wire Spi_clk;
wire Spi_mosi;
wire Spi_miso;
wire Cs_output;
SPI_Interface
# (
.Value_divide (4))
SPI_inst
(
//-----------------內部介面------------------
.Clk (clk_50m),
.Rst_n (rst_n),
.CPOL (1),
.CPHA (0),
.CS_input (1),
.Send_en (Send_en),
.Data_send (Data_send),
.Read_en (Read_en),
.Data_recive (Data_recive),
//------------------外部介面------------------
.Spi_clk (Spi_clk),
.Spi_mosi (Spi_mosi),
.Spi_miso (Spi_miso),
.Cs_output (Cs_output)
);
assign Spi_miso = Spi_mosi;
initial begin
Send_en <= 0;
Data_send <= 0;
#400;
Send_en <= 1;
Data_send <= 8'haf;
#20
Send_en <= 0;
#800;
Send_en <= 1;
Data_send <= 8'h55;
#20
Send_en <= 0;
end
endmodule
2、模擬結果
兩倍分頻：
四倍分頻：
八倍分頻：
CPOL=1、CPHA=1；
CPOL=1、CPHA=0；
CPOL=0、CPHA=0；
CPOL=0、CPHA=1；
結論：模擬實驗初步成功，能夠滿足SPI通信的基本要求。
